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IRLR8503PbF
Table 3 and Table 4 describes the event during the various charge segments and shows an approximation of losses during that
period.
Table 3 – Control FET Losses
P COND = I RMS × R DS ( on )
Description
Conduction Losses associated with MOSFET on time. I RMS is a function of load
Loss current and duty cycle.
Segment Losses
2
P QGS 2 ≈ V IN × I L ×
Q GS 2
P QGD ≈ V IN × I L ×
Q GD
Gate Drive
Loss
Switching
Loss
Losses associated with charging and discharging the gate of the
MOSFET every cycle. Use the control FET Q G .
Losses during the drain voltage and drain current transitions for every full cycle.
Losses occur during the Q GS2 and Q GD time period and can be simplified by using
Q switch .
P IN = V G × Q G × ?
I G
I G
× ?
× ?
P SWITCH ≈ V IN × I L
Q SW
I G
× ?
Output
Loss
Losses associated with the Q OSS of the device every cycle when the control
FET turns on. Losses are caused by both FETs, but are dissipated by the control P OUTPUT =
FET.
Q OSS
2
× V IN × F
Table 4 – Synchronous FET Losses
P COND = I RMS × R DSon
Description
Conduction Losses associated with MOSFET on time. I RMS is a function of load current and
Loss duty cycle.
Gate Drive Losses associated with charging and discharging the gate of the MOSFET every
Loss cycle. Use the Sync FET Q G .
Segment Losses
2
P IN = V G × Q G × ?
Switching
Loss
Generally small enough to ignore except at light loads when the current reverses
in the output inductor. Under these conditions various light load power saving
techniques are employed by the control IC to maintain switching losses to a
negligible level.
P SWITCH ≈ 0
turns on. They are caused by the synchronous FET, but are dissipated in the control P OUTPUT =
Output
Loss
Losses associated with the Q OSS of the device every cycle when the control FET
FET.
Q OSS
2
× V IN × ?
Typical PC Application
The IRLR8103V and the IRLR8503 are suitable for
Synchronous Buck DC-DC Converters, and are optimized
for use in next generation CPU applications. The
IRLR8103V is primarily optimized for use as the low side
synchronous FET (Q2) with low R DS(on) and high CdV/dt
immunity.The IRLR8503 is primarily optimized for use as
the high side control FET (Q2) with low cobmined Qsw and
R DS(on) , but can also be used as a synchronous FET. The
IRLR8503 is also tested for Cdv/dt immunity, critical for
the low side socket. The typical configuration in which
these devices may be used in shown in Figure 7.
4
IRLR8503
Control FET (Q1)
1 x IRLR8103 V or
or 2 x IRLR8503
Synchronous
FET (Q2)
Figure 7 . 2 & 3-FET solution for
Synchronous Buck Topology.
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